The present invention relates to a method of wafer alignment, defect detection, and analysis for semiconductor wafers. More specifically, this invention relates to methods of locating defects on both processed and unprocessed semiconductor wafers, thereby allowing analysis and defect review tools to navigate directly to previously identified defects for examination at high magnification.
In order to remain competitive, semiconductor manufacturers must continually increase integrated circuit performance while reducing cost. A factor in cost reduction and performance enhancement is the reduction of device dimensions, thereby increasing circuit density on an integrated circuit chip. Cost reductions are also achieved by increasing the yield. The number of good chips obtained from a wafer determines the yield. As may be expected, defective chips that are discarded increase the cost of the remaining nondefective chips.
It is important to identify and review defects on blank wafer surfaces because the presence of defects has the potential to decrease yield. Furthermore, it is important to review wafer defects throughout the fabrication process continually monitoring the wafer for defects introduced during each step of manufacturing.
Existing methods of defect inspection utilize a number of detectors which have been developed to measure the number, location, and size of defects on a wafer surface. One type of detector is known as a laser surface particle detector (LSPD). However, the LSPD by itself does not always provide sufficient information regarding the magnitude and cause of defects. In almost all cases, the defects must be further analyzed to identify the source of the defect and its magnitude. A scanning electron microscope (SEM) equipped with an energy-dispersive X-ray spectroscopy (EDS) system works well for measuring the details of defects in a wafer surface. However, due to the extremely small field of view of the SEM, defects are difficult to find on a blank wafer surface. Existing techniques use a combination of the LSPD to locate defects on the wafer surface and the SEM/EDS system to analyze the defects. A number of combined systems are used in the semiconductor industry to quantify defects in wafer systems. However, as chip technology improves and device geometry shrinks, the need to find smaller and smaller defects increases. This requires an analysis system that is able to detect and analyze smaller defects. A major problem in the analysis of small defects is the problem of locating the defects with the SEM after they have been identified with the LSPD. When the wafers are transferred between various machines they become misaligned. Frequently, the wafer misalignment is so great that the SEM may not use the minimum magnification to observe the defects. The current industry standard is that a minimum of 1500xc3x97 magnification is usually required on an SEM in order to see a 0.6xcexc defect. For typical cathode-ray tube (CRT) screens, this translates to a field of view of 70xc3x9770 microns. This means that a defect""s position must be known with an error of less than 35-40xcexc in order for an SEM to find the defect. If the SEM is positioned too far from the defect, analysis time is wasted searching for defects. This position error is a major problem and, if the position error exceeds 100xcexc, an inordinate amount of time must be taken searching for defects.
Presently, position error is reduced by having the integrated circuit (IC) manufacturer scribe fiducial marks on blank wafers after receiving the wafers from the wafer manufacturer. By scribing two or more fiducial marks on the wafer surface, the number and position of the fiducial marks can be determined. These fiducial marks in conjunction with locations of known defects are used as the basis of a coordinate reference system. A typical system used to determine the location of defects on a blank wafer is disclosed in U.S. Pat. No. 5,847,821 of Tracy, et al., which is incorporated by reference herein. The method of Tracy requires that blank wafers received by the IC manufacturer from the wafer manufacturer be scribed with fiducial marks. Typically, this is accomplished by using a laser-scribing tool. These marks form the basis of coordinate mapping and defect location schemes. There are disadvantages to having the IC manufacturer add fiducial marks. The process of scribing the fiducial marks is a time-consuming process which increases manufacturing time and costs. Furthermore, the fiducial marks may take up valuable wafer surface space and reduce the area available for fabricating circuit structures, thereby reducing yield. Additionally, during processing the fiducial marks or reference defects may become covered by deposited materials (e.g. lithographic patterns, metallization layers, oxide layers, dielectric layers, etc.), making them useless as reference points. Also, the very process of scribing fiducial marks contributes to the formation of additional defects.
Therefore, what is needed is a method of aligning a semiconductor wafer on one or more inspection and analysis tools without the need for added fiducial marks. What is also needed is a method for identifying the position on the wafer of defects and for an analysis tool to be able to rapidly locate the defects for analysis without need for the addition of fiducial marks.
The present invention is directed to a method for aligning semiconductor wafers in inspection and analysis tools. The method of the present invention also allows an inspector to orient a wafer in an inspection or analysis tool then navigate directly to defects on an unprocessed (or processed) wafer at high magnification. The method uses the manufacturer""s scribe as a coordinate reference, alleviating the need for the IC manufacturer to laser scribe additional reference marks (fiducial marks).
Unprocessed (xe2x80x9cblankxe2x80x9d) wafers are received by the IC manufacturer having a manufacturer""s identification number (the xe2x80x9cscribexe2x80x9d) scribed onto their surface. Furthermore, wafers are typically manufactured having a flat edge or a notch at the wafer""s edge (the flat and notch will collectively be referred to hereinafter as a xe2x80x9cnotchxe2x80x9d). The unprocessed wafer is placed in an inspection tool. The position of a wafer notch is determined and the wafer is roughly aligned. Subsequently, the scribe is located under low magnification. A software algorithm is used to define the area occupied by the scribe. The positions of the scribe and notch are determined and the coordinates of their locations are recorded using the software algorithm. The inspection tool is then used to locate a first set of defects. The locations of these defects are determined and coordinates mapped relative to the notch and scribe by the software algorithm. The wafer is then transferred to an analysis tool, which rapidly performs calculations using the position coordinates of the scribe and/or the notch to correctly orient the wafer. Using the position coordinates of the scribe and the position coordinates of the notch, the analysis tool navigates directly to the position of each of the first set of defects at high magnification.
The present invention is also directed to a method of defect analysis in which an unprocessed wafer can be sent through a series of selected process tools and second and subsequent sets of additional defects may be determined and analyzed.
The present invention is also directed to a method of defect analysis in which a wafer may be analyzed after individual processing steps and the presence of additional defects may be determined and analyzed.
The present invention may be better understood upon consideration of the following detailed description, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art, the embodiments of the present invention are shown and described by way of illustration of the principles of the invention. As will be realized, the invention is capable of other embodiments and its several features are capable of modifications in various aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not restrictive.